Multi-level cache with associativity collision compensation
US10437732B2 · kind B2 · utility
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23Claims
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Key dates
| Filing date | Dec 14, 2016 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Jun 9, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/608
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a processor includes at least one core and a first cache memory including a first plurality of sets having a first plurality of cache lines and associated metadata to store address information, recency information and a first indicator to indicate whether the cache line is associated with an oversubscribed set of a second cache memory. A first cache controller may be configured to base an eviction decision with regard to a first set of the first plurality of sets including a first cache line at least in part on the first indicator of the first cache line. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.