Calibration on high-speed IO interfaces
US10437753B1 · kind B1 · utility
1Cited by
3References
10Claims
0Family size
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Key dates
| Filing date | Aug 23, 2018 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Aug 23, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure relate to a computer-implemented method. According to the method, a series of valid control codes for a calibration stage in a channel corresponding to a plurality of calibration cycles are acquired from the calibration logic. The acquired valid control codes are analyzed to obtain changing characteristics for the calibration stage in the channel. The calibration logic for the calibration stage in the channel is adjusted in one or more subsequent calibration cycles based on the changing characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.