Hardened white box implementation 1
US10438513B2 · kind B2 · utility
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1References
19Claims
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Assignee
Inventors
Key dates
| Filing date | Oct 30, 2015 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Jul 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/16
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The invention provides a processor device having an executable, white-box-masked implementation of a cryptographic algorithm implemented thereon. The white-box masking comprises an affine mapping A, which is so designed that every bit in the output values w of the affine mapping A depends on at least one bit of the obfuscation values y, thereby attaining that the output values w of the affine mapping A are statistically balanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.