Method and apparatus for multi-level setback read for three dimensional crosspoint memory
US10438659B2 · kind B2 · utility
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14References
26Claims
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Key dates
| Filing date | Jul 17, 2018 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Jul 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.