Erasing method and storage medium
US10438673B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 27, 2018 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Apr 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are an erasing method, erasing apparatus for memory cells and a storage medium to perform erase loops with a more appropriate erasing voltages. The method includes performing erase loops on a target erasing block by sequentially using first erasing voltages Vn; and when a predetermined condition is reached, proceeding to perform erase loops on the target erasing block by sequentially using second erasing voltages Um until the target erasing block is successfully erased. Vn=V1+(n−1)×d1, where n denotes erase loop counts of the first erasing voltages, n is an integer greater than or equal to 1, and V1 and d1 are positive numbers. Um=Vn+(m−1)×d2, where m denotes erase loop counts of the second erasing voltages, m is an integer greater than or equal to 2, and d2 is a positive number not equal to d1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.