Method for manufacturing CMOS structure
US10438854B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2018 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Jun 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0172
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method for manufacturing a CMOS structure. A first gate stack is formed on a semiconductor substrate in a first region. A second gate stack is formed on the semiconductor substrate in a second region. A dopant of a first type is implanted with the first gate stack and the second gate stack as a hard mask to form a lightly-doped drain region of the first type. A dopant of a second type is implanted by using a first mask and with the second gate stack as a hard mask to form a lightly-doped drain region of the second type. The first mask blocks the first region and exposes the second region. When the lightly-doped drain region of the second type is formed, the dopant of the second type over dopes a predetermined region of the lightly-doped drain region of the first type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.