HV converter with reduced EMI
US10438900B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2018 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Mar 29, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high voltage (HV) converter implemented on a printed circuit board (PCB) includes a double diffused metal oxide semiconductor (DMOS) package comprising a lead frame and a main DMOS chip. The lead frame includes a gate section electrically connected to a gate electrode of the main DMOS chip, a source section electrically connected to a source electrode of the main DMOS chip and a drain section electrically connected to a drain electrode of the main DMOS chip. The PCB layout includes a large area source copper pad attached to and overlapping the source section of the DMOS package to facilitate cooling and a small area drain copper pad attached to and overlapping the drain section of the DMOS package to reduce electromagnetic interference (EMI) noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.