Integrally formed bias and signal lead for a packaged transistor device
US10438908B2 · kind B2 · utility
2Cited by
4References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2017 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Nov 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A lead, for a packaged transistor device, having a signal portion and a bias line portion, with the signal portion and the bias line portion each having a proximal end and a distal end. The signal portion and the bias line portions of the lead are integrally formed together as a single conductive component, with the proximal end of the bias line portion integrated into the signal portion of the lead and with the distal ends of the signal portion and the bias line portion physically separate from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.