Display substrate and method of manufacturing the same
US10438974B2 · kind B2 · utility
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1References
7Claims
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Key dates
| Filing date | Jan 27, 2015 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Apr 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to an exemplary embodiment, a display substrate includes a gate metal pattern comprising a gate electrode, an active pattern disposed on the gate pattern and a source metal pattern disposed on the active pattern. The source metal pattern includes a first lower pattern disposed on the active pattern, a second lower pattern disposed on the first lower pattern, a low-resistance metal pattern disposed on the second lower pattern, and an upper pattern disposed on the low-resistance metal pattern. The first lower pattern, the second lower pattern, and the upper pattern each include a material that is the same.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.