Method for manufacturing semiconductor device including step of simultaneous formation of plurality of contact openings
US10438982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2016 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Oct 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes a first opening, a second opening, and a third opening which are formed by performing first etching and second etching. By the first etching, the first insulator is etched for forming the first opening, the second opening, and the third opening. By the second etching, the first metal oxide, the second insulator, the third insulator, the fourth insulator, the second metal oxide, and the fifth insulator are etched for forming the first opening; the first metal oxide, the second insulator, and the third insulator are etched for forming the second opening; and the first metal oxide is etched for forming the third opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.