Photomask layout, methods of forming fine patterns and method of manufacturing semiconductor devices
US10439048B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2018 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Jul 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/027
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming fine patterns including forming a plurality of first sacrificial patterns on a target layer, the target layer on a substrate, forming first spacers on respective sidewalls of the first sacrificial patterns, removing the first sacrificial patterns, forming a plurality of second sacrificial patterns, the second sacrificial patterns intersecting with the first spacers, each of the second sacrificial patterns including a line portion and a tab portion, and the tab portion having a width wider than the line portion, forming second spacers on respective sidewalls of the second sacrificial patterns, removing the second sacrificial patterns, and etching the target layer through hole regions, the hole regions defined by the first spacers and the second spacers, to expose the substrate may be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.