Patent · US Active

Circuit arrangement for an electronic device

US10439605B2 · kind B2 · utility

1Cited by
1References
7Claims
0Family size

Assignee

Inventors

Key dates

Filing dateFeb 2, 2018
Grant dateOct 8, 2019
Priority date
Expiry dateFeb 2, 2038

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH02M7/003
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A circuit arrangement for an electronic device having at least two semiconductor elements of the same type connected in parallel with each other. At least one first semiconductor element has a first characteristic and at least one second semiconductor element has a second characteristic. Each of the two characteristics is defined by at least one power loss. The at least one power loss of the at least one first semiconductor element has a first value, and the at least one power loss of the at least one second semiconductor element has a second value. The two values of the at least one power loss are different.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.