Array substrate, display panel, and display device, including thin film transistor having increased effective length of channel region
US10444585B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 12, 2017 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Apr 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1213
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate, a display panel, and a display device are provided. The array substrate includes a substrate, and a plurality of scanning lines and a plurality of data lines disposed on the substrate. The plurality of scanning lines and the plurality of data lines are insulated and intersected to define a plurality of pixel units. Each pixel unit includes a thin film transistor and a pixel electrode. A gate electrode of the thin film transistor is electrically connected to a scanning line, a source electrode of the thin film transistor is electrically connected to a data line, and a drain electrode of the thin film transistor is electrically connected to the pixel electrode. An effective length of a channel region of the thin film transistor is longer than or equal to one third of a length of the pixel unit along an extension direction of the scanning line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.