Random number generator
US10445068B2 · kind B2 · utility
1Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Sep 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/84
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated random signal generation circuit includes two logic gates, the output of each gate coupled to a respective first input of the other gate via assemblies of delay elements. The respective delays introduced by the assemblies of delay elements are adjustable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.