Execution order block for graphical programming
US10445072B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 10, 2017 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Dec 29, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/455
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphical block diagram can use an execution order block to enforce an execution order for parallel subtrees. A graphical data flow block diagram is generated that includes parallel subtrees. The parallel subtrees can be connected to input pins of the execution order block in the execution order. The parallel subtrees are processed in the execution order before other blocks connected to the parallel subtrees are processed according to the normal execution order of the graphical program. The execution order of the execution order block is not affected by the other blocks, and the normal execution order of the other blocks according to the graphical program is not affected by the execution order of the execution order block. The techniques described herein improve a model-based development platform.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.