Instruction and logic for interrupt and exception handling
US10445204B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2015 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Dec 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/86
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a processor trace logical unit to produce branch execution records from execution of instructions. The processor further includes logic to determine that a condition has occurred on the processor during execution of the instructions. The condition is to include an asynchronous event or a return from a software handler for an asynchronous event. The processor further includes logic to determine whether event tracing is enabled for the processor. The processor also includes logic to generate a control flow event (CFE) packet. The CFE packet is to indicate a type of the condition. The processor further includes logic to generate an indicator of an instruction address that generated the condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.