Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction features
US10445451B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2017 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Jul 1, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. At least one of the plurality of processing elements includes a plurality of control inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.