Integrated circuit for multiple patterning lithography, a computing system and a computer-implemented method for designing an integrated circuit
US10445455B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2017 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Jan 5, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.