Embedded refresh controllers and memory devices including the same
US10446216B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2016 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Sep 14, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embedded refresh controllers included in memory devices and memory devices including the embedded refresh controllers are provided. The embedded refresh controllers may include a refresh counter and an address generator. The refresh counter may generate a counter refresh address signal in response to a counter refresh signal such that the counter refresh address signal may represent a sequentially changing address. The address generator may store information with respect to a hammer address that is accessed intensively and may generates a hammer refresh address signal in response to a hammer refresh signal such that the hammer refresh address signal may represent an address of a row that is physically adjacent to a row of the hammer address. Loss of cell data may be reduced and performance of the memory device may be enhanced by detecting the intensively-accessed hammer address and performing the refresh operation based on the detected hammer address efficiently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.