Method for maximizing power efficiency in memory interface block
US10446254B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | May 3, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller writes a first data test to a memory device through either the host interface or the memory interface at a first voltage level to determine a first write value. The controller reads the first data test written to the memory device through the same interface, either the host interface or the memory interface, at a second voltage level to determine a first read value. The controller then changes the second voltage to a third voltage based on a determination of whether the first read value is equal to the first write value to dynamically alter a working voltage level of the storage device in response to changing process, voltage, and temperature conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.