Low resistance interconnect
US10446439B2 · kind B2 · utility
0Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2015 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Dec 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76871
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment includes an apparatus comprising: a transistor formed on a substrate; and a metal interconnect formed in a dielectric layer above the transistor, wherein: the interconnect comprises a copper layer and a barrier layer that separates the copper layer from the dielectric layer, and the barrier layer comprises tantalum and niobium. Other embodiments are described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.