Semiconductor package
US10446478B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | May 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon; a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; a passivation layer disposed on the connection member; and an underbump metallurgy (UBM) layer embedded in the passivation layer and electrically connected to the redistribution layer of the connection member, wherein the UBM layer includes a UBM pad embedded in the passivation layer, at least one plating layer disposed on the UBM pad and having side surfaces of which at least portions are covered by the UBM pad, and a UBM via penetrating through at least portions of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.