Semiconductor integrated circuit device
US10446492B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | May 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a configuration for ensuring sufficient power supply ability and ESD protection capability for I/O cells in a semiconductor integrated circuit device, without increasing its circuit area. In two I/O cell rows, a pair of I/O cells for supplying a power supply potential or ground potential are connected together via a common power supply interconnect. The I/O cells are arranged so as to overlap with each other in a first direction in which the I/O cells are arranged. The common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to first pads that are located closest in the first direction to the common power supply interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.