Semiconductor integrated circuit device
US10446540B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 5, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Sep 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/911
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.