Enhancement-mode/depletion-mode field-effect transistor GAN technology
US10446544B2 · kind B2 · utility
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1References
24Claims
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Assignee
Inventors
Key dates
| Filing date | Jun 7, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Jun 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/84
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit die having a substrate with a first device stack disposed upon the substrate and a second device stack spaced from the first device stack and disposed upon the substrate is disclosed. The second device stack includes a first portion of a channel layer and a threshold voltage shift layer disposed between the first portion of the channel layer and the substrate, wherein the threshold voltage shift layer is configured to set a threshold voltage that is a minimum device control voltage required to create a conducting path within the first portion of the channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.