Heterostructure power transistor with AlSiN passivation layer
US10446676B2 · kind B2 · utility
1Cited by
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8Claims
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Key dates
| Filing date | Sep 9, 2017 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Sep 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.