Broadband phase locked loop for multi-band millimeter-wave 5G communication
US10447283B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | May 29, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | May 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01Q5/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a phase locked loop (PLL) circuit includes a first voltage controlled oscillator (VCO) to generate a first signal having a first frequency and a second VCO to generate a second signal having a second frequency. The PLL circuit includes a multiplexer coupled to the first VCO, the second VCO, and a feedback loop. The PLL circuit includes a control logic to select either the first VCO or the second VCO using the multiplexer to feed back a signal using the feedback loop, and a phase frequency detector coupled to the first VCO, the second VCO, and the feedback loop, where the phase frequency detector is configured to receive a reference signal and the feedback signal to tracking a frequency and a phase of the first or the second generated signal using the reference signal and the feedback signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.