System and method for an oversampled data converter
US10447294B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2017 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Aug 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/438
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In accordance with an embodiment, a circuit includes a first oscillator having an oscillation frequency dependent on an input signal at a first input, where the first oscillator is configured to oscillate when an enable input is in a first state and freeze its phase or reduce its frequency when the enable input is in a second state. The circuit also includes a first time-to-digital converter having an input coupled to an output of the first oscillator, and a pulse generator having an input coupled to a first clock input of the circuit and an output coupled to the enable input of the first oscillator, where the pulse generator is configured to produce a pulse having pulse width less than a period of a clock signal at the first clock input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.