Patent · US Active

Bypass path loss reduction

US10447323B2 · kind B2 · utility

2Cited by
10References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 10, 2017
Grant dateOct 15, 2019
Priority date
Expiry dateNov 10, 2037

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH04B7/04
  • WIPO fieldTelecommunications
  • WIPO sectorElectrical engineering

Abstract

Aspects of this disclosure relate to reducing insertion loss associated with a bypass path. In an embodiment, an apparatus includes a first switch having at least two throws, a second switch having at least two throws, a bypass path between the first switch and the second switch, and at least one inductor. The at least one inductor is configured to compensate for capacitance associated with the bypass path to cause insertion loss of the bypass path to be reduced.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.