Device and method for ultra-low latency communication
US10447463B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 13, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Jul 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2210/006
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An ultra-low latency communication device includes a clock recovery module, a de-serializer module, an FPGA fabric and a serializer module. The clock recovery module receives an incoming electrical physical layer serial signal and recovers a recovered clock signal therefrom. The de-serializer module converts the incoming electrical physical layer serial signal to an incoming electrical physical layer parallel signal according to driving signals generated based on the recovered clock signal. The FPGA fabric processes the incoming electrical physical layer parallel signal to output an incoming data-link layer parallel signal, receives an outgoing data-link layer parallel signal generated based on electronic information contained in the incoming data-link layer parallel signal, and processes the outgoing data-link layer parallel signal to output an outgoing electrical physical layer parallel signal. The serializer module converts the outgoing electrical physical layer parallel signal to an outgoing electrical physical layer serial signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.