Digital signal receiver and method for controlling signal processing in such digital signal receiver
US10448337B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 23, 2017 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Jun 9, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital signal receiver comprises an iterative decoder configured to decode its input signal using an iterative decoding algorithm, a signal quality detector, configured to detect signal quality of the input signal of the iterative decoder; a power consumption monitor, configured to detect a parameter indicating power consumption of the iterative decoder; a voltage regulator, configured to adjust a supply voltage of the iterative decoder to maintain it within a preset supply voltage range, based on the detected parameter indicating the power consumption of the iterative decoder; and an iteration controller, configured to adjust a maximum iteration number of decoding based on the signal quality of the input signal of the iterative decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.