System and method for shared memory ownership using context
US10452287B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2016 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | May 28, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.