Scheduler for vector processing operator allocation
US10452449B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 10, 2017 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Jan 6, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a plurality of hardware engines and a scheduler circuit. The hardware engines may be configured to process a plurality of vectors using a plurality of operators. The scheduler circuit may be configured to (i) parse a directed acyclic graph into one or more of the operators, (ii) track a plurality of unscheduled operators that have not been allocated to the hardware engines, (iii) track a plurality of statuses of the hardware engines and (iv) allocate at least one of the unscheduled operators to at least one of the hardware engines based on the statuses. The at least one unscheduled operator may be processed in the at least one hardware engine. The scheduler circuit may be implemented solely in hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.