Microprocessor fault detection and response system
US10452493B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2017 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Dec 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/805
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects disclosed in the detailed description include a microprocessor fault detection and response system. The microprocessor fault detection and response system utilizes a hardware-based fault-attack aware microprocessor extension (FAME) and a software-based trap handler for detecting and responding to a fault injection on a microprocessor. Upon detecting the fault injection, the hardware FAME switches the microprocessor from a normal mode to a safe mode and instructs the microprocessor to invoke the software-based trap handler in the safe mode. The hardware-based FAME provides fault recovery information to the software-based trap handler via a fault recovery register (FRR) for restoring the microprocessor to a fault-free state. By utilizing a combination of the hardware-based FAME and the software-based trap handler, it is possible to effectively protect the microprocessor from malicious fault attacks without significantly increasing performance and area overheads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.