Memory controlling device for reconstructing original data using non-blocking code and memory system including the same
US10452531B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 8, 2019 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Mar 8, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system including a memory subsystem and a memory controller is provided. The memory subsystem includes a plurality of first memory modules implemented by a phase-change memory and a second memory module implemented by a memory whose write speed is faster than that of the phase-change memory. The memory controller generates a non-blocking code from a plurality of sub-data into which original data are divided, writes the non-blocking code to the second memory module, writes the plurality of sub-data to the plurality of first memory modules, respectively, and reconstructs the original data from some sub-data of the plurality of sub-data which are read from some of the plurality of first memory modules and the non-blocking code read from the second memory under a predetermined condition at a read request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.