Patent · US Active

Method, system, and computer program product for implementing routing aware placement for an electronic design

US10452807B1 · kind B1 · utility

3Cited by

11References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Karun Sharma · Fremont, US
Nikhil Garg · Faridabad, IN
Juno Lin · Saratoga, US
Subhashis Mandal · Noida, IN
Chandra Prakash Manglani · Sidhauli, IN
Kanaka Raju Gorle · Noida, IN
Henry Yu · Palo Alto, US

Key dates

Filing date	Mar 31, 2017
Grant date	Oct 22, 2019
Priority date	—
Expiry date	Oct 21, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2111/20
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed are techniques for implementing routing aware placement for an electronic design. These techniques identify a block having one or more first pins or interconnects to be inserted into a first layer corresponding to a first set of tracks and identify a second set of tracks on a second layer adjacent to the first layer. One or more candidate locations may be generated on the first layer for the block based in part or in whole upon the first set of tracks. The block may be inserted into a candidate location on the first layer based in part or in whole upon respective costs or routability of the one or more candidate locations with respect to the second set of tracks.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.