Minimum/maximum and bitwise and/or based coarse stencil test
US10453170B2 · kind B2 · utility
4Cited by
30References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2016 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Dec 10, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2210/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus relating to techniques for provision of minimum or maximum and bitwise logic AND or logic OR based coarse stencil tests are described. In an embodiment, metadata (corresponding to a plurality of pixels) is stored in memory. One or more operations are performed on the metadata to generate a stencil result. The one or more operations comprise a bitwise intersection operation or a bitwise union operation and/or a minimum operation or maximum operation. Other embodiments are also disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.