Memory device
US10453510B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2017 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Feb 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N52/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic (SyAF) layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, SyAF layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the SyAF layers to grow in the FCC (111) direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.