Method of manufacturing a CMOS transistor
US10453755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2018 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Jul 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/314
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.