Method and apparatus for forming multi-layered vias in sequentially fabricated circuits
US10453787B2 · kind B2 · utility
0Cited by
3References
11Claims
0Family size
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Key dates
| Filing date | May 20, 2016 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Aug 23, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5226
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic module assembly including a via spanning multiple layers in a wafer based module is described. The electronic module assembly can include a first layer deposited upon a substrate, a second layer deposited on a top surface of the first layer, and the via spanning multiple layers. The via can include a first bottom that is formed on a top surface of the first layer and a first sidewall that upstands from the first bottom and extending at least through the second layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.