Semiconductor memory device having capping pattern defining top surface of air gap
US10453796B2 · kind B2 · utility
3Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2017 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Sep 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5222
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.