Patent · US Active

Short circuit reduction in a ferroelectric memory cell comprising a stack of layers arranged on a flexible substrate

US10453853B2 · kind B2 · utility

0Cited by

4References

6Claims

0Family size

Assignee

Thin Film Electronics ASA · NO

Inventors

Christer Karlsson · Linköping, SE
Olle Jonny Hagel · Linköping, SE
Jakob Nilsson · Säter, SE
Per Bröms · Linköping, SE

Key dates

Filing date	Jul 28, 2016
Grant date	Oct 22, 2019
Priority date	—
Expiry date	Jul 28, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH10D1/696
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A ferroelectric memory cell (1) and a memory device (100) comprising one or more such cells (1). The ferroelectric memory cell comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one ferroelectric memory material layer (7) between said electrodes. The stack further comprises a buffer layer (13) arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (ΔL) occurring in the protective layer (11) and thus preventing said dimensional change (ΔL) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.