Semiconductor packaging structure
US10453956B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2019 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Jun 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.