Inverter with balanced voltages across internal transistors
US10454479B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2018 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Aug 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An inverter includes a first system voltage terminal, a second system voltage terminal, an output terminal, a plurality of P-type transistors, a plurality of N-type transistors, and a voltage drop impedance element. The first system voltage terminal receives a first voltage, and the second system voltage terminal receives a second voltage. The plurality of P-type transistors are coupled in series between the first system voltage terminal and the output terminal. The plurality of N-type transistors are coupled in series between the output terminal and the second system voltage terminal. The voltage drop impedance element is coupled in parallel with a first N-type transistor of the plurality of N-type transistors, and the impedance of the voltage drop impedance element is smaller than the impedance of the first N-type transistor when the first N-type transistor is turned off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.