Segmented resistor architecture for digital-to-analog converters
US10454487B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2018 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Aug 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure describes aspects of segmented resistor architecture for digital-to-analog converters (DACs). In some aspects, a DAC circuit is implemented with a first resistor network coupled to a set of binary code-controlled current sources and a second resistor network that includes a resistor coupled between the first resistor network and an output of the DAC circuit. A set of thermometer code-controlled current sources are coupled to a node of the second resistor network and provide varying amounts of current. This current is scaled based on a resistance of the second resistor network's resistor, which is higher than a resistance of the first resistor network and effective to increase a combined output impedance of the first and second resistor networks. The increase of output impedance reduces noise of the resistor networks that transfers to the output of the DAC circuit, thereby improving signal-to-noise performance of the DAC circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.