Analog-to-digital converter speed calibration techniques
US10454492B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2018 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Jun 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A conversion time and an acquisition time of an ADC can be estimated so that a speed of the ADC can be calibrated. An ADC circuit can perform M bit-trials in its conversion phase and continue performing additional bit-trials in a calibration mode. The ADC can count the number of additional bit-trials performed, e.g., X bit-trials, that occur before the next conversion phase, where additional bit-trials can be considered to be the number of available bit-trials during an acquisition time if the ADC continues performing bit-trials instead of sampling an input signal. The ADC can estimate the conversion time and the acquisition time using M and X. Then, the conversion time of the ADC can be calibrated by adjusting one or more of the comparison time, DAC settling delay, and logic propagation delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.