Mating backplane for high speed, high density electrical connector
US10455689B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2018 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Jul 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10189
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.