Multilayered substrate and method for manufacturing the same
US10455708B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2017 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Nov 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09827
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multilayered substrate in accordance with an aspect of the present disclosure may include an insulating layer, a conductive pattern embedded, at least partially, in the insulating layer, and a bump being electrically connected to the conductive pattern and penetrating the insulating layer. The bump may include a low melting point metal layer having a melting point lower than a melting point of the conductive pattern and a high melting point metal layer having a melting point higher than the melting point of the low melting point metal layer and having a latitudinal cross-sectional area smaller than a latitudinal cross-sectional area of the low melting point metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.