Integrating MEMS structures with interconnects and vias

US10457548B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Kevin Lin · Beaverton, US
• Chytra Pawashe · Portland, US
• Raseong Kim · Hillsboro, US
• Ian A. Young · Portland, US
• Kanwal Jit Singh · Hillsboro, US
• Robert L. Bristol · Portland, US

Key dates

• Filing date: Jun 22, 2015
• Grant date: Oct 29, 2019
• Expiry date: Jun 22, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76897
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.