Low flux and low noise detection circuit
US10458842B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2017 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Apr 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/77
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The detection circuit comprises a detector connected to an integration node. A bias circuit biases the detector between a first bias state and a second floating state. The potential of the integration node is at a target value when the bias circuit biases the detector to the first state and varies when the detector is in floating state. A measurement circuit without charge losses delivers a value representative of the potential present on the integration node N. A transfer circuit of the electric charges performs transfer of the electric charges from a stray capacitor of the photodiode to an integration capacitor. An output terminal delivers a voltage representative of the potential present on the second terminal of the first capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.